An approach for quantifying the impact of not simulating mispredicted paths
نویسندگان
چکیده
We describe an approach and set of tools for quantifying the potential error introduced by not simulating instructions from mispredicted paths in out-of-order speculative superscalar processors. The approach consists of modeling the behavior of programs on out-of-order superscalar processors twice: once by actually simulating the effects of the instructions in the mispredicted paths, and once by stalling instruction fetch until mispredicted branches are resolved. For each case, we measure the performance of the processor in terms of the average number of instructions completed per cycle (IPC), and collect various other statistics regarding the behavior of the program in the presence of mispredicted paths. In addition, in the case of simulating the mispredicted instructions, the first level cache memories are simultaneously modeled with and without the mispredicted memory references, and the additional cache activity in the taken path of the program due to the mispredicted instructions is recorded.
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